Conventional MOS transistors are typically laterally oriented with the two source/drain regions separated by a distance across a top surface of a substrate. In so-called “planar” and “non-planar” transistors, such as a tri-gate or nanowire transistor with a “gate all around” architecture, the first source/drain material is typically the same as that of the second source/drain material because it is difficult to controllably fabricate one of the source/drain materials selectively to the other, particularly in view of the minute lateral spacing between them (e.g., ˜30 nm, or less). As such, achieving lateral FETs with high drive current and/or low leakage currents is becoming increasingly difficult with continued scaling of transistor dimensions.
In vertically oriented MOS transistors (i.e., vertical FETs), a first source/drain is disposed over a second source/drain layer with a gate electrode controlling a channel disposed between the first and second source/drain. Typical vertical FETs have a substantially homogenous crystalline composition, with only dopant species varying, and are fabricated, for example, by implanting a dopant species (e.g., n-type) in a first source/drain region substantially as is done for laterally oriented devices. A vertical pillar of semiconductor is then patterned (e.g., by anisotropic etch) through the implanted source/drain to expose underlying semiconductor, at which point and a second implant is performed to form the second source/drain. Finally, a gate stack is formed. While such vertically oriented transistors may find application in devices where laterally oriented MOS transistors are disadvantaged by other system-level constraints (e.g., in memory devices where vertically-oriented memory structures exist, access transistors may be advantageously oriented in the vertical, as well), the conventional vertical transistor offers little advantage over planar devices with respect to drive current and/or leakage current, etc.